VLSI Design Internship
Learn digital chip design and verification: Verilog, testbenches, FSMs, timing, SystemVerilog, UVM basics, synthesis and the open-source ASIC flow.
What you'll work on
- Level 1: Foundations - VLSI design flow, Digital logic refresher, Install tools and more
- Level 2: Building real features - ALU design, Memory design, UART in Verilog and more
- Level 3: Professional work and capstone - Pipelined processor, UVM introduction, Functional coverage and more
Full syllabus: all 30 graded tasks
These are the actual tasks the internship portal assigns for this domain. You submit each one with proof (a GitHub link or document) and a mentor reviews it.
Level 1: Foundations (12 tasks)
- VLSI design flow. Explain the VLSI flow from specification to RTL, synthesis, place and route, verification and tape-out with a diagram.
- Digital logic refresher. Design and simulate basic gates, a multiplexer, a decoder and a full adder.
- Install tools. Install Icarus Verilog and GTKWave (or use EDA Playground) and simulate a simple module. Commit to a repo named vlsi-internship.
- Verilog basics. Write modules using wire, reg, assign, always blocks and parameters, with a testbench for each.
- Combinational circuits in Verilog. Write a 4-bit adder, comparator and 8:1 mux with testbenches and waveforms.
- Sequential circuits. Write D flip-flops, a shift register and an up/down counter with reset.
- Blocking vs non-blocking. Show with simulation why non-blocking assignments are used in sequential logic.
- Finite state machines. Design a sequence detector FSM (Moore and Mealy) and verify it.
- CMOS basics. Explain how a CMOS inverter works and draw NAND and NOR transistor diagrams.
- Timing basics. Explain setup time, hold time, clock-to-Q and propagation delay with a diagram.
- Number systems in hardware. Implement signed addition and overflow detection in Verilog.
- Simulation debugging. Find and fix three bugs planted in a Verilog design using waveforms.
Level 2: Building real features (10 tasks)
- ALU design. Design an 8-bit ALU with at least 8 operations and a full testbench.
- Memory design. Write a parameterised RAM and a FIFO with full and empty flags.
- UART in Verilog. Implement a UART transmitter and receiver and test them in loopback.
- Clock domain crossing. Explain metastability and implement a two-flip-flop synchroniser.
- Self-checking testbench. Write a testbench that compares outputs with expected values automatically and reports pass/fail.
- SystemVerilog basics. Rewrite a testbench using SystemVerilog classes, randomisation and assertions.
- Synthesis. Synthesise a design with Yosys and read the gate count and report.
- Static timing analysis concept. Calculate slack for a simple path and explain how to fix a setup violation.
- FPGA flow. Run a design on an FPGA board or a simulator flow (Vivado or Quartus free editions) with pin constraints.
- Low-power design. Explain clock gating and power gating and add clock enable logic to a design.
Level 3: Professional work and capstone (8 tasks)
- Pipelined processor. Design a simple pipelined RISC-V or MIPS-like processor core for a few instructions and verify it.
- UVM introduction. Build a basic UVM testbench (driver, monitor, scoreboard) for a simple DUT on EDA Playground.
- Functional coverage. Add coverage to your testbench and reach a coverage goal you define.
- Open-source ASIC flow. Run a small design through the OpenLane flow with the Sky130 PDK (or study a published run) and explain each stage.
- Physical design concepts. Explain floorplanning, placement, clock tree synthesis and routing with example reports.
- Design for testability. Explain scan chains and ATPG and why manufacturing tests are needed.
- Verification plan. Write a verification plan for your processor: features, tests, coverage and sign-off criteria.
- Capstone: verified IP block. Design, verify and synthesise a complete IP block (for example an SPI or I2C controller) with documentation, testbench, coverage and synthesis reports.
Real software work, not just training
Every VLSI Design task is reviewed by our team and saved to your portfolio. Interns who pass the readiness check can take real work from Training Trains, W3AppDevelopers and DomainHostly projects on the Company Work board.
Frequently asked questions
Do I need experience to join the VLSI Design internship?+
Digital electronics knowledge (ECE/EEE). All tools used are free.
What will I do in the VLSI Design internship?+
You complete 30 graded tasks in three levels: foundations, real features, and professional work. Each task is submitted with GitHub or document proof and reviewed. The final capstone is: Capstone: verified IP block.
Do I get a certificate for the VLSI Design internship?+
Yes. After your required tasks are approved, your attendance is above 75% and you pass the proctored final exam, you get a graded completion certificate that anyone can verify at trainingtrains.com/verify.
Can I do the VLSI Design internship online?+
Yes. You can do it fully online from home, or offline at our Erode and Perundurai branches. Tasks, quizzes and mentor reviews are the same in both modes.
Available both online (work from home) and offline at our Erode and Perundurai branches - see the full internship program details for departments, duration, and the application process.