InternshipTools and first-week setup
The tools a VLSI Design intern uses and how to set up your workspace in week one.
These are the main tools for VLSI Design tasks. You do not need all of them on day one; the Level 1 tasks tell you when to install each one.
- Verilog
- Icarus Verilog & GTKWave
- EDA Playground
- SystemVerilog / UVM
- Yosys
- OpenLane
Set up your workspace
- Create a free GitHub account if you do not have one, with a professional username, and set up your LinkedIn profile: every task is submitted with a LinkedIn post.
- Create one repository for the internship, for example vlsi-design-internship, with a README that says who you are and what the repo holds.
- Keep one folder per task, named with the task number and title, so mentors find your work quickly.
- Commit small changes every day with clear messages. Your daily work report uses these commits as proof.
- Never commit passwords, API keys or personal data. Put secrets in a .env file and add it to .gitignore.
Your first tasks
| Task | What to do |
|---|---|
| VLSI design flow | Explain the VLSI flow from specification to RTL, synthesis, place and route, verification and tape-out with a diagram. |
| Digital logic refresher | Design and simulate basic gates, a multiplexer, a decoder and a full adder. |
| Install tools | Install Icarus Verilog and GTKWave (or use EDA Playground) and simulate a simple module. Commit to a repo named vlsi-internship. |
| Verilog basics | Write modules using wire, reg, assign, always blocks and parameters, with a testbench for each. |