The real graded VLSI Design tasks the portal assigns, grouped into three levels.
The portal assigns these VLSI Design tasks. Finish Level 1 before Level 2 and Level 2 before Level 3. Your mentor may mark some tasks as required for the certificate.
Level 1: Foundations (12 tasks)
Task
What to do
VLSI design flow
Explain the VLSI flow from specification to RTL, synthesis, place and route, verification and tape-out with a diagram.
Digital logic refresher
Design and simulate basic gates, a multiplexer, a decoder and a full adder.
Install tools
Install Icarus Verilog and GTKWave (or use EDA Playground) and simulate a simple module. Commit to a repo named vlsi-internship.
Verilog basics
Write modules using wire, reg, assign, always blocks and parameters, with a testbench for each.
Combinational circuits in Verilog
Write a 4-bit adder, comparator and 8:1 mux with testbenches and waveforms.
Sequential circuits
Write D flip-flops, a shift register and an up/down counter with reset.
Blocking vs non-blocking
Show with simulation why non-blocking assignments are used in sequential logic.
Finite state machines
Design a sequence detector FSM (Moore and Mealy) and verify it.
CMOS basics
Explain how a CMOS inverter works and draw NAND and NOR transistor diagrams.
Timing basics
Explain setup time, hold time, clock-to-Q and propagation delay with a diagram.
Number systems in hardware
Implement signed addition and overflow detection in Verilog.
Simulation debugging
Find and fix three bugs planted in a Verilog design using waveforms.
Level 2: Building real features (10 tasks)
Task
What to do
ALU design
Design an 8-bit ALU with at least 8 operations and a full testbench.
Memory design
Write a parameterised RAM and a FIFO with full and empty flags.
UART in Verilog
Implement a UART transmitter and receiver and test them in loopback.
Clock domain crossing
Explain metastability and implement a two-flip-flop synchroniser.
Self-checking testbench
Write a testbench that compares outputs with expected values automatically and reports pass/fail.
SystemVerilog basics
Rewrite a testbench using SystemVerilog classes, randomisation and assertions.
Synthesis
Synthesise a design with Yosys and read the gate count and report.
Static timing analysis concept
Calculate slack for a simple path and explain how to fix a setup violation.
FPGA flow
Run a design on an FPGA board or a simulator flow (Vivado or Quartus free editions) with pin constraints.
Low-power design
Explain clock gating and power gating and add clock enable logic to a design.
Level 3: Professional work and capstone (8 tasks)
Task
What to do
Pipelined processor
Design a simple pipelined RISC-V or MIPS-like processor core for a few instructions and verify it.
UVM introduction
Build a basic UVM testbench (driver, monitor, scoreboard) for a simple DUT on EDA Playground.
Functional coverage
Add coverage to your testbench and reach a coverage goal you define.
Open-source ASIC flow
Run a small design through the OpenLane flow with the Sky130 PDK (or study a published run) and explain each stage.
Physical design concepts
Explain floorplanning, placement, clock tree synthesis and routing with example reports.
Design for testability
Explain scan chains and ATPG and why manufacturing tests are needed.
Verification plan
Write a verification plan for your processor: features, tests, coverage and sign-off criteria.
Capstone: verified IP block
Design, verify and synthesise a complete IP block (for example an SPI or I2C controller) with documentation, testbench, coverage and synthesis reports.
Internship