VLSI Design · Module 7 of 10

Synthesis and timing

Turning RTL into gates and making it fast enough.

📖 Key ideas

Synthesis converts RTL into a gate-level netlist using a standard cell library.
Constraints (SDC) tell tools the clock speed and input/output timing.
Static timing analysis (STA) checks every path meets the clock period.
Setup and hold are the two key timing checks.
Area, timing and power trade off against each other.

💡 Real-life example: Like a relay race: each runner (logic path) must hand over the baton before the whistle (clock edge), not too late (setup) and not too early (hold).

SynthesisConverting RTL into gates

NetlistList of gates and connections

STAStatic timing analysis

Setup timeData must be stable before the clock edge