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VLSI Design · Module 5 of 10

RTL design

Designing chip logic at the register-transfer level.

📖 Key ideas

  1. RTL (register transfer level) describes data moving between registers each clock cycle.
  2. Common blocks: counters, FIFOs, finite state machines (FSMs), arbiters.
  3. An FSM has states and transitions, like a traffic light controller.
  4. Good RTL is synthesizable: tools can turn it into real gates.
  5. Coding guidelines avoid latches, combinational loops and unclear resets.
💡 Real-life example: Like a railway timetable: each tick of the clock, data moves from one station (register) to the next.
RTLRegister transfer level design
FSMFinite state machine
FIFOFirst-in first-out buffer
SynthesizableCan be turned into real gates