InternshipKey terms and common mistakes
The words you will hear in VLSI Design work and the mistakes that most often cost interns approvals.
Key terms
| Term | Meaning |
|---|---|
| VLSI | Very-large-scale integration: putting millions of transistors on one chip |
| RTL | Register-transfer level: hardware described in Verilog or VHDL |
| Verilog | A hardware description language |
| Testbench | Code that tests a hardware design in simulation |
| Synthesis | Turning RTL into a gate-level netlist |
| Timing analysis | Checking signals arrive in time for the clock |
| FSM | Finite state machine: hardware that moves between states |
| FPGA | A chip you can program to act as your design |
Common mistakes to avoid
- Mixing blocking and non-blocking assignments in sequential logic.
- Testbenches that do not check results automatically.
- Latches inferred by missing else branches.
- Ignoring timing reports after synthesis.
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