Smart Parking System

Abstract

1. Introduction

This project is an FPGA-based smart parking management system designed to optimize the process of parking vehicles in a small parking lot. The system uses digital logic and state machines to manage the entry and exit of vehicles, display available parking slots, and control the parking lot's door and full indicators. The project is implemented using Verilog and is designed to run on an FPGA board.

2. Objective

Digital Logic Design course project , Fall of 2024

This project demonstrates how Verilog can be applied to a real-world Internet of Things (IoT) problem.

3. Key Features / Modules

• Entry and Exit Management: The system detects vehicle entry and exit using ultrasonic sensors and updates the parking status accordingly.
• Slot Allocation: The system automatically allocates the nearest available parking slot to incoming vehicles.
• Display System: A 4-digit 7-segment display shows the number of available slots and the best slot for parking.
• Door Control: The system controls the parking lot door, opening it for entry or exit and indicating the door status with a blinking light.
• Full Indicator: When the parking lot is full, a light blinks to indicate no available slots.
• ClockDivider: Generates multiple clock signals from the main clock for different system components.
• Debouncer: Debounces input signals from buttons or sensors to avoid false triggers.
• ParkingFSM: Finite State Machine (FSM) that manages the parking system's states, including entry, exit, and slot allocation.
• ParkingTimer: Tracks the parking duration for each slot and displays the time when a vehicle exits.
• SlotManager: Manages the status of parking slots and updates the number of available slots.

4. Technology Stack

5. System Requirements

General requirements for this technology stack — check the README for exact versions.

• See the project README for exact requirements
• Git (to clone the repository)

6. Installation & Setup

git clone https://github.com/mahanzavari/SmartParkingSystem.git
cd SmartParkingSystem

1. Synthesize the Design: Use an FPGA synthesis tool (e.g., Xilinx Vivado) to synthesize the Verilog code.
2. Upload to FPGA: Load the synthesized design onto the FPGA board.
3. Connect Sensors and Display: Connect the ultrasonic sensor and 7-segment display to the FPGA board as per the pin configuration.
4. Test the System: Use buttons or switches to simulate vehicle entry and exit. Observe the display and door control behavior.

Full setup instructions are in the project README.

7. Future Enhancements

Suggested extensions you can add to make this your own project.

• Add a mobile dashboard using Blynk or Firebase
• Store readings in a cloud database for history charts
• Add alerts via SMS / Telegram when thresholds are crossed

8. Viva / Review Questions

Common questions examiners ask for projects in this domain.

1. Which microcontroller / board and sensors are used and why?
2. How does the device send data (Wi-Fi, MQTT, HTTP, Bluetooth)?
3. Where is the sensor data stored and visualised?
4. How is power consumption managed?
5. How would you secure the device and its communication?

9. Source Code & License

This project is developed by mahanzavari and published on GitHub under the MIT License. Please follow the license terms and credit the original author when you use or modify this code.